Excitation frequency 50Hz, 400Hz and 2.6kHz |
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Resolution: 10 bits, 12 bits, 14 bits |
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High tracking speed |
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Non-standard input is adjustable through external resistance or adjusted at the product input terminal |
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DC voltage output directly proportional to angular velocity |
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Compatible with SDC1700 series of American AD company |
Absolute max. rated value |
Supply voltage Vs: ± 17.5V |
Logical voltage VL: +7V |
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Storage temperature range: -55℃~105℃ |
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Recommended operating conditions |
Supply voltage Vs: ±15V |
5V logic supply voltage VL: +5V |
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Effective value of reference voltage VRef: 11.8V, 26V, 115V |
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Effective value of reference voltage V1*: 11.8V, 26V, 90V |
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Reference frequency f*: 50Hz, 400Hz, 2.6kHz |
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Operating temperature range TA: 0~70℃, -40~+85℃ |
The signals are sent to voltage controlled oscillator after
amplification, phase discrimination and integration filtration, if
θ-φ≠0, the voltage controlled oscillator will output pulse to change the
data in the reversible counter, till θ-φ becomes zero within the
accuracy of the converter, during this process, the converter tracks the
change of input angle θ all the time. For working principle, see Fig.
2. Transfer function: following are parameters for transfer function of HSDC2112 and HSDC2114(400Hz), for other models, please contact the manufacturer directly. |
Fig.2 Block diagram for operating principle of the converter |
In asynchronous reading mode, is set to logic “1” or vacant, if the internal loop is always in stable
state or if the output data is valid shall be determined through the
state of busy signal Busy. When Busy signal is at high level, it
indicates the data is being converted, and the data at this time is
unstable and invalid; when Busy signal is at low level, it indicates the
data conversion has been completed, and the data at this time is stable
and valid. In asynchronous reading mode, Busy output is pulse train of
TTL level, the width between is related to rotational speed. Refer to
time sequence diagram of data transfer Fig. 3. |
Fig.3 Time sequence of data transfer |
6 MTBF curve (Fig. 4) of Synchro to Digital converters or Resolver to Digital Converters (HSDC/HRDC211 Series) |
7 Pin designation (Fig. 5, Table 4) of Synchro to Digital converters or Resolver to Digital Converters (HSDC/HRDC211 Series) |
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Fig. 4 MTBF-temperature curve (Note: according to GJB/Z299B-98, envisaged good ground condition) |
Notes: ① the above structure is suitable for HRDC2114 ② for SDC, no pin S4 ③ for 12-bit device, no pin 13 and 14, for 10-bit device, no pin 11, 12, 13 and 14. Fig.5 Pin designation (Top view) |
Pin |
Symbol |
Function |
Pin |
Symbol |
Function |
1 |
D1 |
Digital outputofbit 1 (MSB) |
15 |
Vel |
Angular velocity voltage output |
2 |
D2 |
Digital outputofbit 2 |
16 |
S4 |
Signal input |
3 |
D3 |
Digital outputofbit 3 |
17 |
S3 |
Signal input |
4 |
D4 |
Digital outputofbit 4 |
18 |
S2 |
Signal input |
5 |
D5 |
Digital outputofbit 5 |
19 |
S1 |
Signal input |
6 |
D6 |
Digital outputofbit 6 |
20 |
Busy |
Busy signal input |
7 |
D7 |
Digital outputofbit 7 |
21 |
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Inhibit signal input |
8 |
D8 |
Digital outputofbit 8 |
22 |
+15V |
+15V Power supply |
9 |
D9 |
Digital outputofbit 9 |
23 |
GND |
Ground |
10 |
D10 |
Digital outputofbit 10 (10-bit LSB) |
24 |
-15V |
-15V Power supply |
11 |
D11 |
Digital outputofbit 11 |
25 |
+5V |
+5V Power supply |
12 |
D12 |
Digital outputofbit 12 (10-bit LSB) |
26 |
RLo |
Low end of reference signal input |
13 |
D13 |
Digital output of bit 13 |
27 |
RHi |
High end of reference signal input |
14 |
D14 |
Digital outputofbit 14 (10-bit LSB) |
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(1) Connection of the converter ±15V, +5V and GND shall be connected to corresponding pins on the converter, notice that the polarities of the power supply must be correct, otherwise, the converter may be damaged. It is recommended to connect 0.1μF and 6.8μF bypass capacitance in parallel between each power supply terminal and ground. Signal and excitation source are allowed to be connected to S1, S2, S3 and S4 and RHi and RLo terminal within an error of 5%. The signal input shall match the phase of the excitation source so that they can be correctly connected with the converter, their phases are as follows: |
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Fig.6 Connecting diagram of typical application |
Fig. 8 is an example of two-speed system composed of the converter.
The two-speed system established on the principle of combination of
coarse and precise measurement has a higher conversion precision, the
figure shows the two-speed conversion system composed of two synchros
(or resolvers) coupled through the gearbox, two SDC converters and a
two-speed processor HTSL19, its output reaches 19 bits. |
Fig.8 Application of two-speed system of SDC |
Fig.7 A feasible external computer interface circuit |
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Fig.9 Digital control servo system |
Fig.10 Outside view of package |